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74FR573 Octal D-Type Latch with 3-STATE Outputs
January 1991 Revised May 2001
74FR573 Octal D-Type Latch with 3-STATE Outputs
General Description
The 74FR573 is a high speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. This device is functionally identical to the 74F573.
Features
s Broadside pinout aids in PC layout s Functionally identical to the 74F373, 74F573 s Outputs have current sourcing capability of 15 mA and current sinking capability of 64 mA s Guaranteed pin-to-pin skew
Ordering Code:
Order Number 74FR573SC 74FR573PC Package Number M20B N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names OE LE D0-D7 O0-O7 Description Output Enable Input (Active-LOW) Latch Enable Input (Active-HIGH) Data Inputs 3-STATE Latch Outputs
(c) 2001 Fairchild Semiconductor Corporation
DS010903
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74FR573
Functional Description
The 74FR573 contains eight D-type latches with 3-STATE output buffers. When the latch enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode, but this does not interfere with entering new data into the latches.
Function Table
Inputs OE L L L H LE H H L X Dn H L X X Output On H L On - 1 High Z State
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
Logic Diagram
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74FR573
Absolute Maximum Ratings(Note 1)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) twice the rated IOL (mA) 4000V
-65C to +150C -55C to 125C -55 to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage 0C to +70C
+4.5V to 5.5V
-0.5V to VCC -0.5 to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH VOL IIH IBVI IIL VID IOD IOZH IOZL IOS ICEX IZZ ICCH ICCL ICCZ CIN Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Input Leakage Test Output Circuit Leakage Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Input Capacitance 26 55 32 8.0 -100 4.75 2.4 2.0 0.55 5 7 -150 -100 Min 2.0 0.8 -1.2 Typ Max Units V V V V V V A A A A V Min Min Min Min Max Max Max Max 0.0 VCC Conditions Recognized HIGH Signal Recognized LOW Signal IIN = -18 mA IOH = -3 mA IOH = -15 mA IIOL = 64 mA VIN = 2.7V VIN = 7.0V VIN = 0.5V Data Inputs VIN = 0.5V Control Inputs IID = 1.9 A, All Other Pins Grounded 3.75 20 -20 -225 50 100 32 65 40 A A A mA A A mA mA mA pF 0.0 Max Max Max Max 0.0 Max Max Max 5.0 AIOD = 150 mV, All Other Pins Grounded VOUT = 2.7V VOUT = 0.5V VOUT = 0.0V VOUT = VCC VOUT = 5.25V All Outputs HIGH All Outputs LOW Outputs 3-STATED
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74FR573
AC Electrical Characteristics
TA = +25C Symbol Parameter Min tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Propagation Delay Dn to On Propagation Delay LE to On Output Enable Time 1.7 1.7 2.6 2.6 2.8 2.8 2.2 2.2 VCC = +5.0V CL = 50 pF Typ 2.9 2.6 6.0 4.3 4.0 5.0 4.0 3.5 Max 4.5 4.5 8.5 8.5 7.4 7.4 6.3 6.3 TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 1.7 1.7 2.6 2.6 2.8 2.8 2.2 2.2 Max 4.5 4.5 8.5 8.5 7.4 7.4 6.3 6.3 ns ns ns ns Units
AC Operating Requirements
TA = +25C Symbol Parameter Min tS(H) tS(L) tH(H) tH(L) tW(H) Setup Time, HIGH or LOW Dn to LE Hold Time, HIGH or LOW Dn to LE LE Pulse Width HIGH 1.0 1.0 2.5 2.5 5.0 VCC = +5.0V CL = 50 pF Typ -0.4 -0.7 0.9 0.6 2.7 Max TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 1.0 1.0 2.5 2.5 5.0 Max ns ns ns Units
Extended AC Electrical Characteristics
TA = 0C to +70C VCC = +5.0V Symbol Parameter CL = 50 pF Eight Outputs Switching (Note 3) Min tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tOSHL (Note 5) tOSLH (Note 5) tOST (Note 5) Pin-to-Pin Skew for HL Transitions Pin-to-Pin Skew for LH Transitions Pin-to-Pin Skew for HL/LH Transitions Output Disable Time Propagation Delay Dn to On Propagation Delay LE to On Output Enable Time 1.7 1.7 2.6 2.6 2.8 2.8 2.2 2.2 Max 5.7 5.7 9.8 9.8 9.6 9.6 7.3 7.3 1.3 1.3 3.0 Min 3.4 3.4 4.5 4.5 Max 8.1 8.1 12.3 12.3 ns ns ns ns ns ns ns TA = 0C to +70C VCC = +5.0V CL = 250 pF (Note 4) Units
Note 3: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase, i.e. all LOW-to-HIGH, HIGH-to-LOW, 3-STATE-to-HIGH, etc. Note 4: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 5: Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW, (tOSHL), LOW-to-HIGH, (tOSLH) or any combination of HIGH-to-LOW and/or LOW-to-HIGH, (tOST). Specifications guaranteed with all outputs switching in phase.
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74FR573
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
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74FR573 Octal D-Type Latch with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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